Switching converters are widely used due to their high efficiency and simple internal structure. FIG. 1 schematically illustrates a prior art switching converter 10. The switching converter 10 comprises a control circuit 100 and a switching circuit 110. The switching circuit 110 comprises at least a power switch M1. The power switch M1 has a first terminal, a second terminal and a control terminal. The switching circuit 110 converts an input voltage VIN to an output voltage VOUT according to a control signal CTRL. The switching circuit 110 may apply different types of topology, such as buck converter, boost converter, buck-boost converter, fly-back converter, and other switching converters.
The control circuit 100 comprises an error amplifier 101, a comparator 102, a logic circuit 103, a current sensing circuit 104 and an oscillator 105.
The error amplifier 101 has a first input terminal, a second input terminal and an output terminal. Based on a reference signal VREF received at the first input terminal and the output voltage VOUT received at the second input terminal, the error amplifier 101 is operable to generate an amplified error signal VEAO at the output terminal. In another embodiment, the error amplifier 101 generates the error signal VEAO based on the reference signal VREF and a feedback signal indicating a load current IOUT of the switching converter 10.
The comparator 102 has a first input terminal, a second input terminal and an output terminal. The comparator 102 generates a first logic signal VL1 at the output terminal based on a comparison result between the error signal VEAO received at the first input terminal and a current sensing signal RFLTI received at the second input terminal. The current sensing signal RFLTI could reflect a current flowing through the power switch M1 or the inductor L. In the illustrated embodiment in FIG. 1, the current sensing signal RFLTI is generated by a current sensing circuit 104 that is configured to detect the current flowing through the power switch M1.
The logic circuit 103 has a first input terminal, a second input terminal and an output terminal. The logic circuit 103 generates a switching signal CTRL at the output terminal based on the first logic signal VL1 received at the first input terminal and the second logic signal VL2 received at the second input terminal. In the illustrated embodiment in FIG. 1, the second logic signal VL2 is a clock signal provided by the oscillator 105.
DC-DC converter 10 could provide a stable output voltage since the error amplifier 101 regulates the output voltage VOUT to a value substantially equal to the value of the reference signal VREF. In some applications, the value of the reference signal VREF may be relatively low (e.g. 200 mV) while an offset voltage (OFFSET) of the error amplifier 101 could be dozens of mill volts (e.g. 50 mV). So, the error of the output voltage VOUT or load current IOUT may be up to 25%. In addition, the noise of the input transistor of the error amplifier 101 would be amplified and reflected on the output voltage VOUT or load current IOUT. Reducing the error of the output voltage caused by the offset voltage or noise of the error amplifier 101 becomes a big challenge.